module ram_r_w
#(parameter WIDTH_ADDR = 64, WIDTH_DATA = 64, DEPTH_DATA = 256)
(
    input clk,
    input reset,
    input ena,
    input [3:0] mem_select_signal,

    input [WIDTH_ADDR - 1:0] addr,
    input [WIDTH_DATA - 1:0] wdata,
    output reg [WIDTH_DATA - 1:0] rdata
);

    reg [WIDTH_DATA - 1:0] mem[0:DEPTH_DATA - 1];
    //integer i;
    initial begin
                $readmemb("~oscpu/mycpu/rtl/data.txt", mem);
            end

    always @(posedge clk) begin
        if(reset) begin
            //for(i = 0;i < DEPTH_DATA;i = i + 1) begin
            //    mem[i] <= 64'd0;
            //end
            
        end else if(ena) begin
            case(mem_select_signal)
                4'b0001 : begin
                    mem[addr][7:0] <= wdata[7:0];
                end
                4'b0010 : begin
                    mem[addr][15:0] <= wdata[15:0];
                end
                4'b0100 : begin
                    mem[addr][31:0] <= wdata[31:0];
                end
                4'b1000 : begin
                    mem[addr] <= wdata;
                end
            endcase
        end
    end

    always @(posedge clk) begin
        if(reset) begin
            rdata <= 64'd0;
        end else begin
            rdata <= mem[addr];
        end
    end

endmodule
